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Digital electronics / Hardware description language / Static timing analysis / Verilog / Electronic engineering / Electronic design automation / Standard Delay Format


Document Date: 1997-07-30 16:59:35

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File Size: 194,44 KB

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Company

OVI OVI / /

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Facility

OVI headquarters / Port Delays / /

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IndustryTerm

synthesis tools / internet e-mail / technology parameters / /

Organization

ASIC / /

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ProgrammingLanguage

Verilog / /

Technology

ASIC / Verilog / /

SocialTag