The Semantics of x86-CC Multiprocessor Machine Code Susmit Sarkar1 Scott Owens1 Tom Ridge1

First Page		Document Content
Date: 2012-09-10 07:41:01 Computing Computer architecture Software engineering X86 architecture Computer memory Low-level programming language Spinlock X86 Assembly language Memory barrier Memory ordering Exit		The Semantics of x86-CC Multiprocessor Machine Code Susmit Sarkar1 Scott Owens1 Tom Ridge1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Download Document from Source Website File Size: 285,42 KB Share Document on Facebook

	x86-64 Machine-Level Programming∗ Randal E. Bryant David R. O’Hallaron September 9, 2005 Intel’s IA32 instruction set architecture (ISA), colloquially known as “x86”, is the dominant instruction DocID: 1toW9 - View Document
	x86-64 Machine-Level Programming∗ Randal E. Bryant David R. O’Hallaron September 9, 2005 Intel’s IA32 instruction set architecture (ISA), colloquially known as “x86”, is the dominant instruction DocID: 1rBoh - View Document
	System V Application Binary Interface x86-64TM Architecture Processor Supplement Draft Version 0.21 Edited by Jan Hubicka , Andreas Jaeger2 , Mark Mitchell3 1 DocID: 1ryr4 - View Document
	CS:APP2e Web Aside ASM:X87: X87-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron June 5, 2012 DocID: 1ru2k - View Document
	CS:APP Web Aside DATA:IA32-FP: Intel IA32 Floating-Point Arithmetic∗ Randal E. Bryant David R. O’Hallaron June 5, 2012 DocID: 1rpCG - View Document