| Document Date: 2010-02-25 20:19:41
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City ROM / / Company IBM / Intel / Microsoft / / / Event Product Recall / Product Issues / / Facility X11 library / / IndustryTerm software system / ordinary processors / dynamic optimization systems / cooperative hardware/software control / software translation / external user software / processor-specific software translation layer / software/hardware / particular hardware / performance monitoring tools / aggressive register allocation algorithms / flexibility to processor / lowlevel device / arbitrary operating systems / long-term solutions / compiler technology / compilerspecific solutions / signal-processing codes / alias analysis algorithms / system software / software systems / processor chip / software-controlled mechanisms / information to hardware / arbitrary software / basic cooperative hardware/software mechanisms / runtime software requirements / cooperative software/hardware mechanisms / arbitrary hardware / application software / removal algorithm / online translation / runtime instrumentation tools / runtime systems / hardware processor / hardware processors / online use / implementation-specific software translation layer / software translation layer / user-space applications / cooperative hardware/software design / external software / on-chip / memory management / processor hardware / database services / software control / field-sensitive algorithms / superscalar processors / / OperatingSystem AS/400 / Linux / OS/400 / Solaris / POSIX / / Organization U.S. Securities and Exchange Commission / University of Illinois / / Person Portability As / Urbana-Champaign / Vikram Adve Chris Lattner Michael / Anand Shukla Brian Gaeke / / Position Manager Code Generation Profiling Static/Dynamic Optimization Storage I−ISA code Profile info Optional / translator / Application Software Operating System Kernel V−ISA Execution Manager / execution model for the V-ISA / LLVA execution manager / Fisher / Processor−specific translator / / Product special LLVA / / ProgrammingLanguage Java / Java bytecode / R / C / V / C++ / / Technology virtual machine / translator components I−ISA Hardware Processor / Linux / Crusoe / CISC processors / VISC processor / removal algorithm / processor chip / hardware processor / operating system / operating systems / ROM on-chip / aggressive register allocation algorithms / alias analysis algorithms / compiler technology / VLIW processor / flash memory / Java / IA-32 hardware processors / caching / Processor−specific translator Hardware Processor / /
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LLVA: A Low-level Virtual Instruction Set Architecture Vikram Adve Chris Lattner Michael Brukman Anand Shukla Brian Gaeke Computer Science Department University of Illinois at Urbana-Champaign {vadve,lattner,brukman,ashu