Monitoring Performance and Power for Application Characterization with the Cache-aware Roofline Model Diogo Ant˜ao, Lu´ıs Tani¸ca, Aleksandar Ilic, Frederico Pratas, Pedro Tom´as, and Leonel Sousa INESC-ID / Institu

Source URL: www.inesc-id.pt

• Computer architecture
• Computing
• Computer engineering
• Concurrent computing
• Central processing unit
• Thread
• Scheduling
• Kernel
• Roofline model
• CPU cache
• Multi-core processor
• ARC

Method for designing modulo {2n ± k} Binary-to-RNS converters Hector Pettenghi1 , Ricardo Chaves1,2 and Leonel Sousa1,3 1 2

Source URL: www.inesc-id.pt

• Computer arithmetic
• Modular arithmetic
• Residue number system
• 2N
• Mathematics
• Integer sequences
• Discrete mathematics
• Number theory

TOWARDS GPU HEVC INTRA DECODING: SEIZING FINE-GRAIN PARALLELISM Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa INESC-ID, IST, Universidade de Lisboa Rua Alves Redol 9, Lisboa, Portugal {diego.souza,

Source URL: www.inesc-id.pt

• Computing
• Video compression
• Data compression
• Video
• ISO standards
• Videotelephony
• MPEG
• Computer file formats
• High Efficiency Video Coding
• Coding tree unit
• Deblocking filter
• Graphics processing unit

CURRICULUM VITAE LEONEL A. HUNT, M.D. ADDRESS: EDUCATION High School:

Source URL: www.huntspine.com

• Medicine
• Surgery
• Clinical medicine
• Neurosurgery
• Spinal fusion
• Scoliosis
• Orthopedic surgery
• NuVasive
• Orthopedic surgeons
• Andrew C. Hecht
• Todd J. Albert

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation Nuno Roma and Leonel Sousa Instituto Superior Técnico / INESC-ID, Lisboa, Portugal Abstract:

Source URL: www.inesc-id.pt

• Central processing unit
• Computing
• Computer engineering
• Computer architecture
• Parallel computing
• Processor register
• Inter frame
• Vector processor
• Video compression
• ISO standards

Comments of the Final Proof Reading of the paper “Efficient Method for designing Modulo {2n ± k} Multipliers” Hector Pettenghi, Sorin Cotofana and Leonel Sousa 8th of November 2013 This document contains our comment

Source URL: www.inesc-id.pt

Configurable M -factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design Gabriel Falcao∗1,2 , Marco Gomes1,2 , Vitor Silva1,2 , Leonel Sousa3,4 and Joao Cacheira2 1 Instituto

Source URL: www.inesc-id.pt

• Error detection and correction
• Coding theory
• Low-density parity-check code
• Digital Video Broadcasting
• DVB-S2
• Forward error correction
• Turbo code
• Tanner graph
• Noisy-channel coding theorem

SchedMon: A Performance and Energy Monitoring Tool for Modern Multi-cores Lu´ıs Tani¸ca, Aleksandar Ilic, Pedro Tom´as, and Leonel Sousa INESC-ID/IST, Universidade de Lisboa, Lisbon, Portugal {Luis.Tanica,Aleksandar.

Source URL: www.inesc-id.pt

• Software optimization
• Profilers
• Parallel computing
• Performance management
• System administration
• Profiling
• Thread
• Benchmark
• Standard Performance Evaluation Corporation
• Multi-core processor
• Business transaction management
• Perf

Joint Collaboration Efforts of Academia and the Software Industry for the Promotion of Usability Arturo Rivera - UNIS Leonel Morales - URL

Source URL: www.clihc.org

• Humancomputer interaction
• Technical communication
• Usability
• Capability Maturity Model Integration
• Software engineering
• Software quality
• Software

Method for designing Multi-Channel RNS Architectures to prevent Power Analysis SCA Hector Pettenghi† , Jude Angelo Ambrose‡ , Ricardo Chaves† , and Leonel Sousa† † INESC-ID, IST Universidade de Lisboa Lisboa, P

Source URL: www.inesc-id.pt

• 2N
• Residue number system
• Factorial
• Rectangular function