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Central processing unit / Computer memory / Microprocessors / CPU cache / Cache / Cell / Benchmark / Loop nest optimization / Parallel computing / Computer hardware / Computer architecture / Computing


Document Date: 2006-02-28 10:38:47

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Company

IBM / /

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Facility

FPU’s pipeline / FP opera / IBM T. J. Watson Research Center / /

IndustryTerm

interconnect network / computational-bound algorithm / system software stack / bank / systems-on-a-chip / intrachip synchronization hardware / software threads / sparse-matrix vector product / software thread / particular target applications / sparse matrix-vector product / manufacturing technology / unbalanced processing / compiler technology / software simulation environment / communications hardware / near-future silicon technology / computation-bound algorithm / system software / /

MarketIndex

FFT / SPARSE / /

OperatingSystem

Unix system / GNU / POSIX / /

Organization

MIT / /

Person

George Alm´asi / Thomas J. Watson / Derek Lieber / Henry S. Warren / Jr. / Monty Denneau / /

Position

hardware architect / architect / /

ProgrammingLanguage

FP / C++ / /

ProvinceOrState

Manitoba / New York / /

Technology

computational-bound algorithm / computation-bound algorithm / chip design / floating point unit / silicon technology / Unix system / Introduction Multiprocessor systems-on-a-chip / system-on-a-chip / paging / 0218 Abstract Multiprocessor systems-on-a-chip / simulation / operating systems / Cyclops processors / same chip / compiler technology / Cyclops chip / /

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