<--- Back to Details
First PageDocument Content
Cryptography / Integer sequences / Integer factorization algorithms / Primality tests / Safe prime / Finite fields / RSA / Prime number / Strong prime / Blum integer / Trial division / Quadratic sieve
Date: 2016-08-10 03:08:02
Cryptography
Integer sequences
Integer factorization algorithms
Primality tests
Safe prime
Finite fields
RSA
Prime number
Strong prime
Blum integer
Trial division
Quadratic sieve

The Million-Key Question—Investigating the Origins of RSA Public Keys Petr Švenda, Matúš Nemec, Peter Sekan, Rudolf Kvašňovský, David Formánek, David Komárek, and Vashek Matyáš, Masaryk University https://www

Add to Reading List

Source URL: www.usenix.org

Download Document from Source Website

File Size: 869,71 KB

Share Document on Facebook

Similar Documents

02157 Functional Programming - Sequences

02157 Functional Programming - Sequences

DocID: 1rsIU - View Document

How Euler Did It by Ed Sandifer Formal Sums and Products July 2006 Two weeks ago at our MAA Section meeting, George Andrews gave a nice talk about the delicate and beautiful relations among infinite sums, infinite produc

How Euler Did It by Ed Sandifer Formal Sums and Products July 2006 Two weeks ago at our MAA Section meeting, George Andrews gave a nice talk about the delicate and beautiful relations among infinite sums, infinite produc

DocID: 1rnYz - View Document

MATH 802: ENUMERATIVE COMBINATORICS ASSIGNMENT 2 KANNAPPAN SAMPATH Facts Recall that, the Stirling number S(k, n) of the second kind is defined as the

MATH 802: ENUMERATIVE COMBINATORICS ASSIGNMENT 2 KANNAPPAN SAMPATH Facts Recall that, the Stirling number S(k, n) of the second kind is defined as the

DocID: 1rlQh - View Document

Mathematics Grade 6 Student Edition  G6 Playlist: Finding Greatest Common Factors and Least

Mathematics Grade 6 Student Edition G6 Playlist: Finding Greatest Common Factors and Least

DocID: 1rgZE - View Document

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 10, OCTOBERwhere n is the stage gain, f is the clock frequency, VDD is the supply voltage, CCLK is the clock capacitance, N is the num

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 10, OCTOBERwhere n is the stage gain, f is the clock frequency, VDD is the supply voltage, CCLK is the clock capacitance, N is the num

DocID: 1rcVq - View Document