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The finite state automaton based pipeline hazard recognizer and instruction scheduler in GCC Vladimir N. Makarov Red Hat
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Document Date: 2004-08-29 18:00:00

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File Size: 95,95 KB

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RTL / Intel / Red Hat / /

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IndustryTerm

simplest solution / ready and enough processor / software pipelining / dual instruction issue processor / issue processor / target processors / comb vector algorithm / dual issue processor / deterministic devices / /

MarketIndex

SLALOM / /

OperatingSystem

GNU / /

Organization

presence_set UNIT / exclusion_set UNIT-NAMES UNIT / absence_set UNIT / define_cpu_unit UNIT / /

Position

recognizer and instruction scheduler / same instruction scheduler / instruction scheduler / /

ProgrammingLanguage

C / /

Technology

Some processors / Itanium2 processors / comb vector algorithm / dual issue processor / SPARC processors / cloning / same processor / target processors / dual instruction issue processor / improved processor / issue processor / ready and enough processor / /

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