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Cache / CPU cache / Central processing unit / Computer memory / Marc Snir / Multi-core processor / Bill Gropp / Xeon / Intel Core / Computing / Parallel computing / Computer hardware


Torsten Hoefler ETH Zürich Friday, April 4, 2014 3:00 pm Lindley Hall, Rm. 102
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Document Date: 2014-03-31 11:00:15


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Company

Cache-Coherent SMP Systems / Scalable Parallel Computing Laboratory / Intel / /

Country

United States / /

Facility

University of Illinois / Lindley Hall / Scalable Parallel Computing Laboratory / /

IndustryTerm

large-scale parallel applications / parallel algorithms / cache coherency protocols / /

Organization

Blue Waters Directorate / University of Illinois / /

Person

Hermann von Helmholtz / Marc Snir / Bill Gropp / Shlomo Moran / William Kramer / /

Position

Assistant Professor / co-chair of the collective operations working group / /

ProvinceOrState

Illinois / /

Technology

cache coherency protocols / simulation / /

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