Back to Results
First PageMeta Content
Reduced instruction set computing / VAX / Central processing unit / Very long instruction word / Benchmark / Computer architecture / Computing / Instruction set architectures


The LIFE Family of High Performance Single Chip VLIWs Gerrit A. Siavenburg, Philips Research Palo Alto Andrew S. Huang, Carnegie Mellon University1 Yen C. Lee, Philips Research Palo Alto
Add to Reading List

Document Date: 2013-07-27 22:44:28

Open Document

File Size: 374,52 KB

Share Result on Facebook

City

Palo Alto / /

Company

IBM / Philips / Motorola / /

Facility

STORE BRANCH JUMp / /

IndustryTerm

non-trivial systems / prototype chip / unit technology / /

OperatingSystem

GNU / /

Organization

Carnegie Mellon / Department of Electrical / /

Person

Gerrit A. Siavenburg / Andrew S. Huang / /

Position

parallel representation Scheduler / General / /

Product

lllde16 Pushing / LIFE-1 / /

Technology

2.4 HOT Chips / 9 LIFE-1 prototype chip / 2.8 HOT Chips / CONSTunlt ALU units DATAMEM BRANCH delay REGISTER unit technology / algorithmically non-trivial systems HOT Chips / instruction memory HOT Chips / LIFE-1 family prototype Block diagram Chip / /

SocialTag