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Central processing unit / CPU cache / Cache / Software optimization / Memory hierarchy / R10000 / Lookup table / Memory disambiguation / R8000 / Computer memory / Computing / Computer hardware


Journal of Instruction-Level Parallelism[removed]Submitted 10/02; published 4/03
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Document Date: 2003-04-27 18:43:27

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File Size: 342,26 KB

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City

Pittsburgh / /

Company

IBM / EDU Computer Architecture Laboratory / /

/

Facility

Carnegie Mellon University / load/ store / /

IndustryTerm

parallel applications / well-synchronized and scalable applications / relaxed memory systems / directory cache coherence protocol / directives enabling software / shared-memory applications / uniprocessor systems / mechanisms to look up remote processor / speculative processor / otherwise allowing hardware / larger systems / /

MarketIndex

NAS / SPEC / /

NaturalFeature

Instruction Stream / /

Organization

SC SC / AI Access Foundation / Carnegie Mellon University / /

Person

Babak Falsafi / /

Position

L2 controller / queue head / memory controller / head / controller / /

Product

SC / /

ProgrammingLanguage

RC / Split-C / /

ProvinceOrState

Pennsylvania / South Carolina / /

Technology

16 processors / one processor / artificial intelligence / modified processor / fluid dynamics / simulation / Sequential Consistency / directory cache coherence protocol / /

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