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City Job / / Company IBM / Sun Microsystems / ACM Intl / Intel / / / Event FDA Phase / / Facility Safe Store / Computer Science University of Illinois / / IndustryTerm per-line coherence protocol / speculative protocol / Software transformations / directory-based cache coherence protocol / system-wide speculative protocol / successor chips / per-processor / compiler technology / successor processors / layer protocol / self-contained speculation protocols / invalidation-based cache coherence protocol / shared-memory systems / speculative parallelization protocol / non-speculative chip / software schemes / distributed speculative protocol / 4processor chips / cache coherence protocol / conventional invalidation-based cachecoherence protocol / baseline coherence protocol / speculation protocol / / OperatingSystem L3 / / Organization Perfect Club / National Science Foundation / F. Mart´ınez / and Josep Torrellas Department / University of Illinois / / Person Table / / Position network controller / Vp / version Vp / recent version Vp / L2 cache controller / representative / Controller / / Product CMPs / Safe Load / Safe Store / L0-L15 / L2 / DSMC3D / L1 / Section / / ProgrammingLanguage FP / / ProvinceOrState Illinois / / Technology speculation protocol / Per-Word State The protocol / conventional invalidation-based cachecoherence protocol / speculative CMP protocol / speculative protocol / 4processor chips / distributed speculative protocol / CMP protocol / system-wide speculative protocol / directory-based cache coherence protocol / non-speculative chip / local processors / cache coherence protocol / speculative CMP technology / successor chips / compiler technology / CMP / 16 processors / MAJC chip / 4 processors / self-contained speculation protocols / 3.2 Protocol / 2.6 Commits Our protocol / baseline coherence protocol / successor processors / invalidation-based cache coherence protocol / layer protocol / Simulation / virtual memory / conventional / per-line coherence protocol / speculative parallelization protocol / simplified protocol / /
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Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors Marcelo Cintra, Jose´ F. Mart´ınez, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-C