Back to Results
First PageMeta Content
ECC memory / RAM parity / Dynamic random-access memory / Memory scrubbing / Error detection and correction / BIOS / Parity bit / Triton II / Power-on self-test / Computer memory / Computer hardware / Computing


Error Correction Control and Parity BIOS Implementation Example
Add to Reading List

Document Date: 1998-05-15 04:14:29

Open Document

File Size: 25,40 KB

Share Result on Facebook

Company

Initialize Hardware / Intel Corporation / REQUIREMENTS AND INTEL CHIPSET SOLUTIONS / PIIX3 82430HX Memory / /

Facility

South Bridge / North Bridge / /

IndustryTerm

production memory controller chips / 82430HX chip / memory bank / memory controller chip / system software / manageability applications / 82440FX chips / desktop management software / /

Person

J. Carter Added / SERR SMI / Yoke Polished / /

Position

memory controller / 82430HX memory controller / controller / /

Product

Parity / /

ProgrammingLanguage

C / /

Technology

South Bridge chips / RAM / 82430HX chip / South Bridge chip / two production memory controller chips / board design / operating system / memory controller chip / 82440FX chips / /

SocialTag