| Document Date: 2013-08-26 16:12:52
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City C. Stack / / Company A. Hardware / Bluespec Inc / RTL / Intel / / / Event Reorganization / Product Issues / FDA Phase / / Facility D Q lockup / port FIFO / Srinivas Devadas Massachusetts Institute of Technology / / IndustryTerm on-chip network / deadlock-free protocol / adjacent routers / migration infrastructure / directory coherence protocols / thread migration infrastructure / remote-access/migration protocol / given protocol / coherence protocols / test equipment / physical chip / shared address space in hardware / using fast hardware / large-core-count chips / level applications / coherence protocol / directory-based coherence protocol / dual predictor solution / fine-grained thread migration infrastructure / cache coherence protocols / energy / on-chip networks / Off-chip / instruction-granularity decision algorithm / hardware-level thread migration protocol / shared-memory processor / interconnect network / simplified hardware coherence protocols / transistor technology / remote cache access protocol / optimized protocols / software-based approaches / overall memory access protocol / identical networks / energy analysis / higher-level protocol / rule applications / credit-based protocol / conventional directory protocols / / Organization Massachusetts Institute of Technology / ASIC / / Person Processor / S. V. Adve / V / Morgan Kaufmann / Myong Hyon Cho / Srinivas Devadas / / Position guard / simple cache controller / programmer / / Product EM / bypass rule / L1 / / ProgrammingLanguage Verilog / / Technology directory-based protocol / FPGA / chip design / basic MSI protocol / Distributed cache coherence protocols / shared-memory processor / hardware-level thread migration protocol / remote-access/migration protocol / directory-based coherence protocol / conventional directory protocols / two protocols / deadlock-free protocol / SRAM / transistor technology / shared memory / 2 Solo Processor / EM2 chip / 45nm ASIC technology / VHDL / pdf / overall memory access protocol / coherence protocols / instruction-granularity decision algorithm / ASIC / Verilog / higher-level protocol / Flow Control / credit-based protocol / G. Module complexity comparison NoC router / coherence protocol / given protocol / caching / simplified hardware coherence protocols / directory coherence protocols / simulation / sequential consistency / remote cache access protocol / physical chip / B. System verification With evolving VLSI technology / / URL http /
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Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine Keun Sup Shim*, Mieszko Lis*, Myong Hyon Cho, Ilia Lebedev, Srinivas Devadas Massachusetts Institute of Technology, Cambridge,