| Document Date: 2011-07-07 08:25:09 Open Document File Size: 66,37 KBShare Result on Facebook
City Palo Alto / / Company Caches / AMD / HP Labs / I/O / Intel / Microsoft / / Currency pence / / / Facility University of Toronto / / IndustryTerm real-world applications / software prefetch instructions / experimental systems / cache-coherence protocol / Scientific computing papers / parallel applications / tween applications / cache management / software performance / modity hardware / hardware packet routers / suitable hardware / online optimizations / resource management / commodity hardware / commodity systems / hardware/software interface / cache coherence protocol / software polling / message-passing processor / heavyweight inter-processor / / OperatingSystem Linux / Microsoft Windows / / Organization U.S. Securities and Exchange Commission / University of Toronto / / Person Dean Tullsen / Livio Soares / David Patterson / Timothy Roscoe / / Position representative / / Technology IA-32 message-passing processor / FPGA / heavyweight inter-processor / cache-coherence protocol / Linux / simulation / operating system / hardware packet routers / shared memory / cache coherence protocol / operating systems / / URL http /
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