| Document Date: 2013-01-31 17:59:40
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City Austin / / Company BP / Graph Connected Comp / Intel / / Currency pence / / / Facility Courant Institute / University of Texas / / IndustryTerm basic algorithms / sequential cache efficient algorithms / given algorithm / usurpation site / processor algorithm / idle processors / computing / parallel algorithm / in-place algorithm / / Organization NYU / New York / National Science Foundation / Courant Institute / University of Texas / / Person Vijaya Ramachandran / Richard Cole / / Position scheduler / RWS scheduler / oblivious scheduler / / ProvinceOrState Texas / New York / / Technology processor algorithm / SPMS sorting algorithm / 2 HBP Algorithms / given algorithm / sequenced HBP algorithm / 1 recursive HBP algorithm / 1 Algorithm / parallel algorithm / HBP algorithms / HBP algorithm / 2 HBP algorithm / Backer protocol / For HBP algorithms / Multithreaded Algorithms / shared memory / 0 Algorithm / idle processor / in-place algorithm / /
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Revisiting the Cache Miss Analysis of Multithreaded Algorithms ⋆ Richard Cole1 and Vijaya Ramachandran2 1 Computer Science Dept., Courant Institute, NYU, New York, NY 10012.