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Transaction-level modeling / Embedded microprocessors / Joint Test Action Group / OpenRISC / Universal asynchronous receiver/transmitter / Embedded system / Coupling / System on a chip / Catapult C / Electronic engineering / Electronics / SystemC


Building a Loosely Timed SoC Model with OSCI TLM 2.0 A Case Study Using an Open Source ISS and Linux 2.6 Kernel Jeremy Bennett
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Document Date: 2013-01-16 23:54:44

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File Size: 1,61 MB

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San Francisco / /

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Creative Commons / Embecosm Limited / /

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Germany / United States / United Kingdom / Wales / /

Facility

Or1ksim Library / Terminal Module Class Definition / Terminal Module Class Implementation / /

IndustryTerm

on-chip networks / software examples / software ideas / level software models / large embedded software systems / silicon chips / embedded software / software development / /

OperatingSystem

Mac OS / Linux / GNU / /

Organization

Department of Integrated Circuit Design / Technische Universität Braunschweig / OSCI TLM / /

Person

Jeremy Bennett Embecosm / Robert Günzel / /

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author / original author / Logger / JTAG logger / engineer / GNU General Public License / /

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Java / Verilog / C / C++ / /

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Nova Scotia / California / /

Technology

Verilog / Java / Linux / silicon chips / JTAG / VHDL / Integrated Circuit / UART / /

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www.embecosm.com / http /

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