Back to Results
First PageMeta Content
Computer memory / Transaction processing / Compiler construction / Concurrency / Programming language design / Consistency model / Sequential consistency / Memory model / Linearizability / Computing / Software engineering / Computer architecture


SEPTEMBERWRL Research ReportShared Memory
Add to Reading List

Document Date: 2006-10-01 20:57:19


Open Document

File Size: 183,72 KB

Share Result on Facebook

City

Palo Alto / Cambridge / /

Company

IBM / Digital Equipment Corporation / The Western Research Laboratory / Technical Report Distribution DEC Western Research Laboratory / Texas Instruments / /

Country

United States / /

Currency

pence / /

/

Facility

University Avenue Palo Alto / Stanford University / USA The Western Research Laboratory / Rice University / University of Wisconsin-Madison / /

IndustryTerm

chaotic algorithms / individual processors / shared memory systems / hardware-based shared-memory systems / uniprocessor hardware / higher performance since such algorithms / arbitrary processor / system software design / coherence protocol / parallel systems / cache coherence protocols / system software / language processing / update coherence protocol / interconnection network / mainstream high-performance computer systems / hardware-based sharedmemory systems / research / individual processor / higher performance systems / computing / machine hardware / multi-processors / cache coherence protocol / /

MusicGroup

the Network / /

Organization

Rice University / Houston / National Science Foundation / Systems Research Center / Rice University / Network Systems Lab / Department of Electrical and Computer Engineering / Stanford University / University of Wisconsin / /

Person

Kourosh Gharachorloo / Sarita V. Adve / Sarita V. Adve Kourosh Gharachorloo / /

Position

system designer / P1 P2 Read Data t3 Read Head t2 General Interconnect P1 Write Head / head of task / designer / t3 Read Head t2 General Interconnect P1 Write Head t1 Write Data t4 Head / P1 Write Head t3 Write Data t2 P2 General Interconnect Read Head t4 Head / buffer P1 P2 Read Data t3 Read Head / programmer / /

ProvinceOrState

Texas / Wisconsin / California / Massachusetts / /

SportsLeague

Stanford University / /

Technology

Alpha / shared memory system / three processors / two processors / arbitrary processor / individual processor / Shared Memory / cache coherence protocol / cache coherence protocols / based coherence protocol / data caching / caching / update coherence protocol / sequential consistency / /

URL

http /

SocialTag