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Boolean algebra / Electronic design automation / Formal methods / Bioinformatics / Boolean network / Logic / Boolean satisfiability problem / Circuit / Model checking / Theoretical computer science / Applied mathematics / Mathematics


SAT-Based Complete Don’t-Care Computation for Network Optimization Alan Mishchenko and Robert K. Brayton Department of EECS University of California, Berkeley {alanmi, brayton}@eecs.berkeley.edu
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Document Date: 2004-12-03 17:46:16


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Fujitsu / CNF / N. Saluja S. P. / MVSIS Group / Intel / /

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Microelectronics Center / EXTRA library / EECS University of California / /

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don’tcare computation algorithm / binary networks / binary network / industrial tools / deterministic networks / classical algorithm / logic networks / large industrial networks / window construction algorithm / sub-network / nondeterministic multi-valued networks / multilevel network / non-deterministic multi-valued networks / multi-level networks / nondeterministic multi-valued network / same method to larger networks / multi-valued don’t-care computation algorithm / search algorithm / non-deterministic networks / /

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Windows XP / /

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UC Berkeley / University of California / Berkeley / Robert K. Brayton Department / Microelectronics Center of North Carolina / /

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Robert K. Brayton / A. Kuehlmann / V / Alan Mishchenko / /

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L / R / C++ / /

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North Carolina / /

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TFO / /

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BDD-based algorithms / SAT-based don’tcare computation algorithm / RAM / search algorithm / window construction algorithm / windowing algorithm / corresponding BDD-based algorithm / classical algorithm / multi-valued don’t-care computation algorithm / simulation / CAD / /

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