| Document Date: 2010-09-16 09:55:04
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City Santos / F. R / / Company Cryptographic Hardware / Integrated Systems / ITT / John Wiley and Sons / Reconfigurable Hardware / Xilinx / / Currency pence / / Facility Register store Montgomery Constant / Imperial College / store S / Register store Constant / / IndustryTerm public key algorithm / security applications / embedded hard-processors / prime number algorithms / security systems / hardware device / primality test algorithms / extended algorithms / on-chip processors / probabilistic primality test algorithm / hard and soft processors / technology independent hardware / software implementation / computing / soft-processor / parallel processing elements / firewall processors / Internet Mersenne Prime Search / area-limited embedded applications / technology dependent / / NaturalFeature FSL channel / / Organization Imperial College London / Trial Division / Ashley Brown Department of Computing / Croucher Foundation / / Person Ashley Brown / O. Rabin / Ray C.C. Cheung / / Position designer / / ProgrammingLanguage Hardware Description Language / / ProvinceOrState Prince Edward Island / / PublishedMedium Journal of Number Theory / IEEE Transactions on Computers / / Technology Word Radix-2 Montgomery Multiplication Algorithm / FPGA / MWR2MM algorithm / RAM / Chip Design / XC2V1000 FPGA chip / proposed customisable MicroBlaze processor / Rabin-Miller algorithm / hard and soft processors / SYSTEM-ON-A-CHIP / smart card / on-chip processors / Montgomery algorithms / Montgomery algorithm / VHDL / XC2V1000-4FG456C FPGA chip / prime number algorithms / embedded PowerPC processor / Cryptography / 7 System-on-a-Chip / public key / Rabin-Miller probabilistic primality test algorithm / prime number validator Algorithm / Firewall processors / System-on-Chip / Virtex-II Pro chip / low cost Spartan XC3S2000-4-FG900 chip / public key algorithm / low cost XC3S2000 FPGA chip / primality test algorithms / 4 embedded hard-processors / parallel processing / soft MicroBlaze processor / been explored using the embedded PowerPC processor / / URL http /
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A SCALABLE SYSTEM-ON-A-CHIP ARCHITECTURE FOR PRIME NUMBER VALIDATION Ray C.C. Cheung and Ashley Brown Department of Computing, Imperial College London, United Kingdom Abstract This paper presents a scalable SoC architect