Transactional IPC in Fiasco.OC Can we get the multicore case verified for free? Till Smejkal, Adam Lackorzynski, Benjamin Engel and Marcus Völp Operating Systems Group Technische Universität Dresden, Germany

Source URL: www.mpi-sws.org

• Computing
• Computer architecture
• Concurrency control
• Software
• Transaction processing
• Transactional memory
• Microkernel
• Software transactional memory
• Transactional Synchronization Extensions
• L4 microkernel family
• Rock
• Mach

Implementing a Blocked Aasen’s Algorithm with a Dynamic Scheduler on Multicore Architectures Grey Ballard∗ , Dulceneia Becker† , James Demmel∗ , Jack Dongarra†‡§ Alex Druinsky¶ , Inon Peled¶ , Oded Schwart

Source URL: www.cs.huji.ac.il

• Algebra
• Linear algebra
• Mathematics
• Numerical linear algebra
• LU decomposition
• Matrix
• Block matrix
• Rank
• QR algorithm

A Generic Algorithm Template for Divide-and-conquer in Multicore Systems Carlos H. Gonz´alez and Basilio B. Fraguela Depto. de Electr´onica e Sistemas Universidade da Coru˜na A Coru˜na, Spain {cgonzalezv, basilio.fra

Source URL: www.des.udc.es

• Computer programming
• Software engineering
• Computing
• C++
• Concurrent programming languages
• Parallel computing
• Theoretical computer science
• Application programming interfaces
• Algorithmic skeleton
• Recursion
• Divide and conquer algorithms
• Algorithm

Adaptive Matrix Transpose Algorithms for Distributed Multicore Processors John C. Bowman and Malcolm Roberts Abstract An adaptive parallel matrix transpose algorithm optimized for distributed multicore architectures runn

Source URL: www.math.ualberta.ca

• Algebra
• Mathematics
• Matrices
• Linear algebra
• Parallel computing
• Numerical linear algebra
• In-place matrix transposition
• Permutations
• Transpose
• Message Passing Interface
• Cache-oblivious algorithm
• Matrix

Programmazione di Sistemi Multicore - Risultati appello del 13 gennaio 2016 Parte 2 Docente: Irene Finocchi CASSARO COMO DEODATI

Source URL: twiki.di.uniroma1.it

Distributed Queues in Shared Memory Multicore Performance and Scalability through Quantitative Relaxation Andreas Haas Thomas A. Henzinger

Source URL: www.cs.uni-salzburg.at

• Abstract data types
• Concurrency control
• Scheduling algorithms
• Operations research
• Computing
• Concurrent computing
• Business
• Queue
• Double-ended queue
• FIFO
• Scheduling
• Non-blocking algorithm

1 Oversubscription on Multicore Processors Costin Iancu, Steven Hofmeyr, Filip Blagojevi´c, Yili Zheng Lawrence Berkeley National Laboratory Berkeley, USA

Source URL: crd.lbl.gov

• Computing
• Parallel computing
• Computer programming
• Software engineering
• OpenMP
• Multi-core processor
• Thread
• Standard Performance Evaluation Corporation
• Hyper-threading
• NAS Parallel Benchmarks
• POSIX Threads
• Scheduling

Call for Papers The 2010 International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2May 21-23, 2010, Busan, Korea General Co-Chairs

Source URL: cse.stfx.ca

• Parallel computing
• Computing
• Computer programming
• Concurrency computer science)
• Multi-core processor
• Symmetric multiprocessing
• Thread
• Parallel algorithm

How Model-Based Design Simplifies the Debugging of Many-Core Systems Iuliana Bacivarov Computer Engineering and Networks Laboratory, ETH Zürich 1st International Workshop on Multicore Application Debugging (MAD) 2013, 1

Source URL: www.mad-workshop.de

• Computing
• Parallel computing
• Tile
• Debugging
• Embedded system
• Multi-core processor
• Thread
• STR
• ETH Zurich
• Computer engineering

MAD2013 Multicore debugging from a SW compiler perspective Marco Roodzant, ACE Associated Compiler Experts

Source URL: www.mad-workshop.de

• Software
• Computer programming
• Computing
• Compiler construction
• Programming language implementation
• Parallel computing
• Debuggers
• Debugging
• Compiler
• GNU Debugger
• Transputer
• ARC