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SYNERGISTIC PROCESSING IN CELL’S MULTICORE ARCHITECTURE EIGHT SYNERGISTIC PROCESSOR UNITS ENABLE THE CELL BROADBAND
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Document Date: 2008-03-03 12:42:24

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IBM / Toshiba / Rambus / Sony Computer Entertainment / SPE I/O / /

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Local store Local / Local store SMF SMF SMF SMF SMF SMF SMF SMF / /

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data parallel computing / elaborate alignment network / computation-intensive applications / software pipelining / software-controlled data-alignment approach / data-parallel processing / data-parallel processing engine / system services / vector processing / data processing / high-volume data-processing tasks / vector media exten / software abstraction / cryptography algorithms / data-processing-intensive applications / digital media / unsolvable computing problems / reduced-instruction-set computing / scalar processing / dynamic prediction algorithm / vector media extensions / bypass networks / desktop systems / heterogeneous chip / data-parallel computing / test chip / data-intensive processing / /

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IEEE Computer Society / /

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Michael Gschwind / H. Peter Hofstee Brian Flachs Martin / Memory / Yukio Watanabe Toshiba Takeshi Yamazaki / Brian Flachs Martin Hopkins / /

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interface controller / driver / architect / SMF controller / controller / programmer / /

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10 When / /

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Alpha / 2006 13 HOT CHIPS / BROADBAND / nine processors / 2006 17 HOT CHIPS / logic HOT CHIPS / dynamic prediction algorithm / SRAM / virtual memory / operating system / shared memory / operating systems / cryptography algorithms / 2006 15 HOT CHIPS / parallel processing / test chip / /

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