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White Paper Accelerating 20nm Double Patterning Verification with IC Validator Author
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Document Date: 2014-11-07 14:30:19

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File Size: 1,08 MB

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Company

IC Validator Double Patterning Signoff Technology / Synopsys Inc. / Double Patterning Technology / /

Country

United States / /

Event

Force Majeure / /

Facility

Library Prep / Preparation Library / /

IndustryTerm

technology offers / 20nm manufacturing compliance / faster manufacturing closure / 20nm node imaging requirements / technology integration / manufacturing flows / legal mask decomposition solution / manufacturing side / signoff decomposition checking technology / aware density management / optimized design solution / technology file mismatches / manufacturing / 1x metal routing layers / manufacturing closure / alternate solution / violation prevention technology / post-processing techniques / signoff technology / double patterning technology / /

Organization

DPT ADR / /

Person

Stelios Diamantidis / Paul Friedberg / /

Position

Author / designer / cell designer / /

Technology

semiconductor / DPT signoff decomposition checking technology / DPT technologies / DPT-aware placement DPT-aware routing ECO Chip / In-Design technology / violation prevention technology / lithography / DPT-aware technology / signoff technology / double patterning technology / photolithography / integrated circuits / Compiler using In-Design technology / /

URL

www.synopsys.com / http /

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