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Multiprocessor
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#	Item
61	Brute-force determination of multiprocessor schedulability for sets of sporadic hard-deadline tasks TRTheodore P. Baker ∗ Department of Computer Science Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2012-09-05 15:29:37
62	Predicting the Throughput of Multiprocessor Applications under Dynamic Workload Peter Poplavko, Marc Geilen, and Twan Basten This report is an extended version of the following publication. It adds the proofs omitted fro Add to Reading List Source URL: www.es.ele.tue.nl Language: English - Date: 2010-08-14 16:48:41
63	On the Implementation of Pfair-scheduled Multiprocessor Systems by Philip L. Holman Add to Reading List Source URL: www.cs.unc.edu Language: English - Date: 2004-07-01 15:08:10
64	Schedulability Analysis of Multiprocessor Sporadic Task Systems TRTheodore P. Baker∗ Sanjoy K. Baruah Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2012-09-05 15:29:48
65	Global EDF Scheduling of Directed Acyclic Graphs on Multiprocessor Systems RTNS Sophia Antipolis, France Friday 18th October, 2013 Manar Qamhieh1 Add to Reading List Source URL: leat.unice.fr Language: English - Date: 2013-11-08 01:31:08
66	Further improved schedulability analysis of EDF on multiprocessor platforms TRTheodore P. Baker Department of Computer Science Florida State University Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2012-09-05 15:29:39
67	21st International Conference on Real-Time Networks and Systems OctoberA Scheduling Algorithm to Reduce the Static Energy Consumption of Add to Reading List Source URL: leat.unice.fr Language: English - Date: 2013-11-08 01:30:12 Mathematical optimization Multiprocessor scheduling Idle Business Scheduling Planning Operations research
68	Modelling and Validation of Shared Memory Coherency Protocols Abstract We present an analytical model of a cache coherent shared-memory multiprocessor and compare the results obtained with those from an execution-driven Add to Reading List Source URL: pubs.doc.ic.ac.uk Language: English - Date: 2011-11-14 07:29:11 Computer hardware Computer memory Parallel computing CPU cache Cache Central processing unit Memory coherence Cell Bus sniffing Cache coherency Computing Computer architecture
69	Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model JAMES ARCHIBALD and JEAN-LOUP University of Washington BAER Add to Reading List Source URL: ctho.org Language: English - Date: 2005-04-22 14:42:58 Write-once CPU cache Firefly protocol Cache Bus sniffing Cache coherency Computing Computer hardware
70	Supernova - A Multiprocessor Aware Real-Time Audio Synthesis Engine For SuperCollider DIPLOMARBEIT zur Erlangung des akademischen Grades Diplom-Ingenieur/in Add to Reading List Source URL: tim.klingt.org Language: German - Date: 2015-04-26 07:06:20

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