| Document Date: 2003-09-14 15:55:27
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Company IBM / Synopsys / Mentor Graphics / MEI / Intel / Read/Write Bus Memory / / / Event FDA Phase / / Facility BAR BGNT BREQ Figure / Computer Engineering Georgia Institute of Technology Atlanta / BAR BR_BAR BREQ Figure / CPU pipeline / / IndustryTerm incompatible cache coherence protocols / simulation tools / speed devices / digital signal processor / low speed devices / default protocol / prevalent and more computing power / heterogeneous processors / coherence protocols / results software solution / software synchronization / alternate solutions / homogeneous processors / software lock / stack processing / invalidation-based protocols / hardware/software methodology / coherence protocol / distinct protocols / cache coherence hardware / cache coherence protocols / stack processing speed / media processor / heterogeneous multiprocessor systems / pure software solution / snoop hardware / shared bus protocol / embedded processors / bus protocol / few heterogeneous processors / alternate solution / real-time embedded systems / cache coherence protocol / bus protocols / software solution / heterogeneous embedded processors / / Organization Electrical and Computer Engineering Georgia Institute of Technology Atlanta / Hsien-Hsin S. Lee School of Electrical / / Person Figure / Douglas M. Blough / / Position cache controller / Intel486 cache controller / arbiter / Intel486 INV ARTRY ASB HITM BOFF Arbiter / ARM920T nFIQ Snoop logic ARTRY ASB BG_BAR Arbiter / memory controller / Controller / programmer / / Product Write / PowerPC755 / PF3 / AMD64 / ARM920T / Intel486 / IA32 / / ProgrammingLanguage Hardware Description Language / Verilog / / Technology incompatible cache coherence protocols / MSI protocol / invalidation-based protocols / MPEG / MESI protocols / 1 Processor / shared bus protocol / two processors / update-based protocols / Once homogeneous processors / 1.3 MOESI protocol / processor Processor / media processor / 1.1 MSI protocol / system-on-a-chip / default protocol / shared memory / cache coherence protocol / TCP/IP / Integrating processors / MOESI protocols / digital signal processor / coherence protocols / MOESI protocol / heterogeneous embedded processors / modified MESI protocol / cache coherence protocols / Bakery algorithm / few heterogeneous processors / one processor / Verilog / heterogeneous processors / PowerPC bus protocol / invalidation-based protocol / coherence protocol / bus protocols / simulation / SI protocol / MESI protocol / DSP / ASB protocol / 1.2 MESI protocol / Dragon protocol / /
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Supporting Cache Coherence in Heterogeneous Multiprocessor Systems Taeweon Suh, Douglas M. Blough, and Hsien-Hsin S. Lee