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Computer engineering / Parallel computing / Central processing unit / Digital signal processing / SIMD / Microarchitecture / Floating point / Computer / Addition / Computing / Computer architecture / Computer arithmetic


August 5, 1994 To the Graduate School: This thesis entitled "A Reconfigurable Multiprocessor Architecture and its Arithmetic Performance" and written by Mr. Kenneth B. Winiecki, Jr. is presented to the Graduate School o
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Document Date: 2001-12-16 00:05:46

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Facility

Clemson University / /

IndustryTerm

distributed operating systems / data router / information processing / parallel processing / computing / information processing tools / computation equipment / simultaneously-operating processors / word-wide processing element / /

Organization

Graduate School / Clemson University / Integer Division / /

Person

W. B. Ligon / III / Mary Winiecki / L. L. Joiner / D. C. Stanzione / Jr. / Kenneth B. Winiecki / Jr. / K. O. Wichmann / /

Position

advisor / Thesis Advisor / controller / /

ProgrammingLanguage

Verilog / /

ProvinceOrState

Prince Edward Island / /

Technology

technology of computation equipment / Verilog / operating systems / simultaneously-operating processors / parallel processing / data router / /

SocialTag