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Parallel computing / Central processing unit / Microprocessors / Threads / Simultaneous multithreading / Superscalar / Multithreading / Microarchitecture / Multi-core processor / Computing / Computer architecture / Computer hardware


Theme Feature . A Single-Chip Multiprocessor
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Document Date: 1998-03-07 07:33:31

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File Size: 301,20 KB

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City

San Francisco / Palo Alto / New York / /

Company

Rambus / Digital Equipment Corp. / Silicon Graphics / ACM Press / Computer Systems Laboratory / Digital Western Research Laboratory / Intel / Microsoft / 16 Kbytes / /

Currency

USD / /

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Facility

Stanford University / Calvin College / Lance Hammond Basem A. Nayfeh Kunle Olukotun Stanford University / University of Michigan / Hall et al. / University of Cincinnati / /

IndustryTerm

billion-transistor processors / particular bank / cache-coherence protocol / crossbar network / improved compiler technology / integer applications / responsive computing environment / applications / software thread / enough banks / baseline processor / scientific floating-point applications / compiler technology / individual processing cores / active processor / identical processors / processor chip / bank interconnection complexity / parallel applications / multiprocessor-aware operating systems / implementation technology / automatic layout tools / superscalar processor / circuit processing technology offers increasing integration density / billion-transistor chip / validation technology / bank contention / application software increases / multimedia applications / superscalar processors / /

OperatingSystem

Unix / Microsoft Windows / /

Organization

IEEE and the ACM / Calvin College / Secondary / IEEE / Memory / University of Cincinnati / Stanford University / Stanford Univ. / US Defense Advanced Research Projects Agency / the University of Michigan / /

Person

Stanford Univ / Morgan Kaufman / Basem A. Nayfeh Kunle Olukotun / Basem A. Nayfeh / Kunle Olukotun / /

Position

secondary cache controller / candidate in electrical engineering / representative / assistant professor of electrical engineering / member / /

Product

Windows NT / /

ProvinceOrState

New York / Michigan / Mississippi / California / /

PublishedMedium

Microprocessor Report / /

SportsLeague

Stanford University / /

Technology

Alpha / billion-transistor chip / mpeg-2 / chip design / IC technologies / 2-issue baseline processor / mpeg / cache-coherence protocol / fluid dynamics / computational chemistry / IMPLEMENTATION TECHNOLOGY / 4 SMT processors / processor chip / SRAM / operating system / shared memory / operating systems / validation technology / compiler technology / billion-transistor CMOS implementation technology / CMP / real processor / eight processors / billion-transistor processors / one processor / voice recognition / 2-issue superscalar processors / improved compiler technology / remaining processors / SMT processor / 12-issue processor / 3D graphics / Multiscalar Processors / 80 Computer Superscalar Simultaneous multithreading Chip / simulation / SMT processors / superscalar processor / baseline processor / 2-issue processor / lelizing compiler technology / /

URL

http /

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