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Company LSI / RTL / NEC Corporation / / IndustryTerm power reduction technologies / lowskew clock distribution technology / e.g. dummy metal generation / pure physical processing / power estimation tool / individual processing / transistor/wiring manufacturing process / excellent design technology / design technology / it important to use technology / manufacturing / random manufacturing variance / power estimation technology / vector processor / Verification technology / clock gating technology / / Organization 1st Computers Operations Unit / / Position driver / ONO Koki Assistant Manager / Computers Division / KONNO Yoshihiro Manager / Computers Division / SAWANO Tomoki Manager / Computers Division / designer / KUMAZAKI Masahito Assistant Manager / Computers Division / IKAWA Yasuhiro Manager / Computers Division / Assistant Manager / Computers Division / KANAMARU Keisuke Assistant Manager / Computers Division / Manager / Computers Division / / Technology semiconductor / Supercomputer SX-9 Hardware CAD Technology / 37 Supercomputer SX-9 Hardware CAD Technology / power reduction technologies / excellent design technology / clock gating technology / 3.1 Hierarchy Design Technology / Logic Verification Technology / 5.2 Delay Analysis Technology / vector processor / design technology / 4.1 Power Estimation Technology The power estimation technology / 9 6.1 Early Design Verification Technology / lowskew clock distribution technology / two technologies / CAD technology / Simulation / Large-scale Design Technology / Verification technology / Multi-Vth technology / 5.1 High-accuracy Clock Mesh Delay Calculation Technology / 35 Supercomputer SX-9 Hardware CAD Technology / main technologies / Multi-Vth technologies / 4.2 Power Reduction Technology / CAD / / SocialTag 
Supercomputer SX-9 Hardware CAD Technology of the SX-9 KONNO Yoshihiro, IKAWA Yasuhiro, SAWANO Tomoki KANAMARU Keisuke, ONO Koki, KUMAZAKI Masahito Abstract