<--- Back to Details
First PageDocument Content
Computing / Computer architecture / Concurrent computing / Formal methods / Theoretical computer science / Cache coherency / Instruction set architectures / Concurrency / TLA+ / Model checking / Cache coherence / Specification language
Date: 2010-09-11 18:46:20
Computing
Computer architecture
Concurrent computing
Formal methods
Theoretical computer science
Cache coherency
Instruction set architectures
Concurrency
TLA+
Model checking
Cache coherence
Specification language

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

Add to Reading List

Source URL: rjoshi.org

Download Document from Source Website

File Size: 113,32 KB

Share Document on Facebook

Similar Documents

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

DocID: 1xUst - View Document

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

DocID: 1xUq9 - View Document

CACHE COHERENCE DIRECTORIES FOR SCALABLE MULTIPROCESSORS Richard Simoni Technical Report: CSL-TROctober 1992 Computer Systems Laboratory

CACHE COHERENCE DIRECTORIES FOR SCALABLE MULTIPROCESSORS Richard Simoni Technical Report: CSL-TROctober 1992 Computer Systems Laboratory

DocID: 1vmKd - View Document

HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores ∗ Nivedita Sritharan, Anirudh Kaushik, Mohamed Hassan, Hiren Patel November 30, 2017 This technical report provides additio

HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores ∗ Nivedita Sritharan, Anirudh Kaushik, Mohamed Hassan, Hiren Patel November 30, 2017 This technical report provides additio

DocID: 1uMvz - View Document

Predictable Cache Coherence for MultiCore Real-Time Systems Mohamed Hassan, Anirudh M. Kaushik and Hiren Patel RTAS 2017 Motivation: Data sharing in multi-core real-time systems

Predictable Cache Coherence for MultiCore Real-Time Systems Mohamed Hassan, Anirudh M. Kaushik and Hiren Patel RTAS 2017 Motivation: Data sharing in multi-core real-time systems

DocID: 1u5Cm - View Document