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Digital media / Dynamic random-access memory / CPU cache / Memory controller / CAS latency / Memory bandwidth / Alpha 21164 / DIMM / The Berkeley IRAM Project / Computer memory / Computer hardware / Computing


1 A Case for Intelligent RAM: IRAM (To appear in IEEE Micro, AprilA Case for Intelligent RAM: IRAM David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm,
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Document Date: 1997-02-12 03:05:01

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File Size: 87,18 KB

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Mitsubishi / Samsung / Intel / /

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USD / AMD / /

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Facility

Katherine Yelick Computer Science Division/EECS Department University of California / One bar / /

IndustryTerm

actual processor / word processor / energy consumption / memory latency-hiding hardware / fixed energy consumption / on-processor / 1Kbit metal bus needs / less energy / chips / larger chips / energy efficiency / normal solution / lower energy consumption / server systems / desktop systems / Memory systems / metal layers / energy / /

OperatingSystem

L3 / /

Organization

Katherine Yelick Computer Science Division/EECS Department University / University of California / Berkeley / /

Person

Richard Fromm / Randi Thomas / Kimberly Keeton / Neal Cardwell / Thomas Anderson / David Patterson / Katherine Yelick / /

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Position

word processor / external memory controller / memory controller / /

ProvinceOrState

California / /

Technology

semiconductor / Alpha / merged chip / actual processor / 16 processors / just 4 chips / RAM / 1 processor / larger chips / 32 DRAM chips / IRAM processor / cache memory / 16 chips / also 16 chips / same processor / gigabit / SRAM / operating system / DRAM chips / RISC chips / DRAM chip / word processor / fewer DRAM chips / huge individual DRAM chips / same chip / Year Processor / /

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