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Computer memory / Field-programmable gate array / MicroBlaze / Xilinx / CPU cache / Multi-core processor / Dynamic random-access memory / Joint Test Action Group / NetFPGA / Computer hardware / Computing / Electronic engineering


Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures Spyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitris Tsaliagkos, Manolis Katevenis, Dionisios Pnevmatikatos a
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Document Date: 2013-12-23 07:16:59

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File Size: 2,01 MB

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Company

Xilinx DRAM / Formic / Xilinx / Microsoft / /

Currency

USD / /

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Facility

I2 C port / Dimitris Nikolopoulos Institute of Computer Science / RS232 port / port TLB / /

IndustryTerm

large systems / unrealistic software simulation parameters / software simulation / software vs. / software needs / hardware cache coherency protocols / multicore processing / networkon-chip / network-on-chip / multicore systems / message-passing processor / internal network / /

Organization

Dimitris Nikolopoulos Institute of Computer Science / SRAM DRAM Board / US Federal Reserve / IN CPU / Foundation for Research and Technology / European Union / /

Person

SATA MBS MBS MBS MBS / Dimitris Tsaliagkos / SATA GTP SATA MBS MBS / M. Katevenis / V / SATA GTP SATA GTP SATA / George Kalokerinos / /

Position

DRAM controller / guard for any physical layer errors / controller / /

Product

XUPV5-LX110T development system / XUPV5-LX110T / /

ProgrammingLanguage

Verilog / /

Technology

IA-32 message-passing processor / FPGA / SRAM chips / Verilog / flow control / hardware cache coherency protocols / JTAG / board design / 1-Gbit 400-MHz DDR2 SDRAM chip / SRAM / simulation / shared memory / UART / /

URL

www.xilinx.com/univ/xupv5-lx110t.htm / http /

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