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1 Compositional Performance Verification of Network-on-Chip Designs Daniel E. Holcomb, and Sanjit A. Seshia, Senior Member, IEEE
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Document Date: 2014-06-05 21:33:15

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File Size: 3,65 MB

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Company

ABC / Acyclic Networks / Intel / Computer Sciences / /

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Facility

University of California Berkeley / /

IndustryTerm

given network / possible networks / possible xMAS networks / i5 processor / industrial ring interconnection network / credit loop network / cyclic networks / depth-first search / xMAS networks / loop network / industrial-style ring interconnection network / computing / cyclic network / /

MarketIndex

IEEE / /

OperatingSystem

Fork / /

Organization

University of California / Department of Electrical Engineering and Computer Sciences / U.S. Securities and Exchange Commission / /

Person

Sanjit A. Seshia / Daniel E. Holcomb / I NTERCONNECT / /

Position

model network microarchitectures / guard / memory controller / head / /

Product

Time Since Injection / /

ProgrammingLanguage

C++ / /

ProvinceOrState

Qi / /

Technology

RAM / Verilog / flow control / i5 processor / simulation / Quality of Service / Tilera TILE64TM processor / /

URL

http /

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