<--- Back to Details
First PageDocument Content
Digital signal processors / Technology / Instruction set architectures / TriMedia / Nexperia / Digital signal processing / ARM architecture / CPU cache / Media processor / Electronic engineering / Electronics / Philips
Date: 2013-07-27 23:51:46
Digital signal processors
Technology
Instruction set architectures
TriMedia
Nexperia
Digital signal processing
ARM architecture
CPU cache
Media processor
Electronic engineering
Electronics
Philips

Microsoft PowerPoint - HC18.130.S1T3.Home entertainment-quality multimedia experience whilst on the move ΠPhilips Nexperia Mob

Add to Reading List

Source URL: www.hotchips.org

Download Document from Source Website

File Size: 394,61 KB

Share Document on Facebook

Similar Documents

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

DocID: 1rkhA - View Document

BidSwitch DSP/Agency Seat Mapping Overview BidSwitch is an infrastructure layer that serves as a single integration point between SSPs and DSPs, providing our partners with an efficient and transparent way to manage acce

BidSwitch DSP/Agency Seat Mapping Overview BidSwitch is an infrastructure layer that serves as a single integration point between SSPs and DSPs, providing our partners with an efficient and transparent way to manage acce

DocID: 1qf93 - View Document

Chapter 1 CUSTOMIZABLE AND REDUCED HARDWARE MOTION ESTIMATION PROCESSORS Nuno Roma, Tiago Dias, Leonel Sousa Abstract

Chapter 1 CUSTOMIZABLE AND REDUCED HARDWARE MOTION ESTIMATION PROCESSORS Nuno Roma, Tiago Dias, Leonel Sousa Abstract

DocID: 1q2wP - View Document

Microsoft Word - Vimicro_VC3809_PB_IPC_V1.0.doc

Microsoft Word - Vimicro_VC3809_PB_IPC_V1.0.doc

DocID: 1oMhK - View Document