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Digital media / Dynamic random-access memory / CPU cache / Random-access memory / DIMM / Virtual memory / Computer memory / Computer hardware / Computing


VaMV: Variability-aware Memory Virtualization Luis Angel D. Bathen∗ , Nikil D. Dutt∗ , Alex Nicolau∗ , and Puneet Gupta † ∗ School of Information and Computer Science, University of California, Irvine, {lbathen
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Document Date: 2012-01-31 18:44:55


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Company

DRAMs / Hanson / 1GB DRAMs / HP / App1 LP / Layer I. I NTRODUCTION Hardware / /

Currency

pence / /

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Event

Product Issues / /

Facility

University of California / /

IndustryTerm

voltage scaling on-chip / software module / adaptable and tunable software/hardware / multi-core processors / Memory intensive applications / quality sensitive applications / application level solution / 65nm process technology / extra hardware / dynamic memory management / off-theshelf hardware / on-chip / software annotations / /

Organization

School of Information and Computer Science / National Science Foundation / University of California / Los Angeles / LP PEM / U.S. Securities and Exchange Commission / University of California / Irvine / Department of Electrical Engineering / /

Person

Angel D. Bathen / Luis Angel / Alex Nicolau / /

Position

arbiter / programmer / /

Product

Variability / VaMV / VaMVisor / VaMVisor Device / cells / /

Technology

transparently exploiting on-chip / RAM / adpcm / BMP / E-RAID / jpeg / voltage scaling on-chip / Cortex M3 processors / GSM / simulation / SRAM / virtual memory / increased access latency Nominal Vdd On-Chip / 65nm process technology / CMP / /

URL

http /

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