| Document Date: 2013-12-23 07:16:58
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Company Intel / / / Facility Institute of Computer Science / / IndustryTerm on-chip network / system scheduling algorithm / software configuration / application specific coherence protocols / out-of-order-execution processors / particular chip / energy consumption / power estimation tool / partitioned cache-scratchpad on-chip memory systems / software-managed partitions / plain cache energy consumption / optimized lightweight software library / synchronization hardware / virtual networks / virtual network 1GB off-chip / given technology process / aggressive non-blocking coherence protocols / parallel processing / lower energy consumption / appropriate routing algorithms / energy reduction / software notification / stream processing environment / plain hardware / energy / / MarketIndex FFT / TLB / / Organization Universidad Politecnica de Valencia / European Commission / Foundation for Research and Technology / Institute of Computer Science / / Person Giorgos Passas / Christos Sotiriou / M. Alvarez Mesa / George Kalokerinos / Directly Cacheable Addressable (Scratchpad) / George Nikiforos / Georgi Gaydadjiev / Michael Ligerakis / Spyros Lyberis / Xiaojun Yang / Christoforos Kachris / Dimitris Tsaliagos / Alex Ramirez / Federico Silla / / Position cache controller / programming model to data transfers / architect / cache/scratchpad controller / producer / programmer / issue Parameter Cores L1 I/D Caches L2 Caches Coherence Protocol Data Prefetcher Scratchpad RDMA Controller / / Product ORION / / ProgrammingLanguage C / / PublishedMedium the ORION / / Technology 4.3 On-chip / FPGA / appropriate routing algorithms / virtual network 1GB off-chip / aggressive non-blocking coherence protocols / API / 2010 issue Parameter Cores L1 I/D Caches L2 Caches Coherence Protocol Data Prefetcher Scratchpad RDMA Controller Remote Stores Network-on-Chip / particular chip / GEMS MOESI-directory protocol / operating system scheduling algorithm / caching / out-of-order-execution processors / SRAM / simulation / 65nm CMOS technology / operating system / shared memory / application specific coherence protocols / parallel processing / cmp / /
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Explicit Communication and Synchronization in SARC Manolis G.H. Katevenis∗ , Vassilis Papaefstathiou∗ , Stamatis Kavadias∗ , Dionisios Pnevmatikatos∗ , Federico Silla+ , Dimitrios S. Nikolopoulos∗ ∗