Back to Results
First PageMeta Content
Computer memory / Cache / Central processing unit / Microprocessors / CPU cache / Prefetcher / Multi-core processor / Microarchitecture / X86 / Computer hardware / Computing / Computer architecture


Prefetching and Cache Management Using Task Lifetimes Vassilis Papaefstathiou∗ Manolis G.H. Katevenis∗ FORTH-ICS
Add to Reading List

Document Date: 2014-02-26 04:38:59

Open Document

File Size: 458,39 KB

Share Result on Facebook

City

Martonosi / Heraklion / Eugene / Chania / Analysis / /

Company

IBM / Epochbased Cache Management / Intel Corporation / ARM Ltd. / S. McPeak S. P. / Cache Management / Parallel Distributed Systems / HP Laboratories / /

Country

United States / Greece / /

Currency

USD / /

/

Facility

Queen’s University of Belfast Belfast / Technical University of Crete / University of Crete / /

IndustryTerm

on-chip network / minimal software / simulator infrastructure / runtime software / software runtime / virtual networks / multi-core systems / runtime software uses double-buffering / software guidance / coherence protocol / hardware-software approach / energy savings / 32nm technology / energy / static energy measurements / benchmark applications / multicore processors / energy consumption / software-directed prefetching / hardware-software synergy / page-table walking hardware / less energy / virtual network / cooperative hardware/software approach / target stream processing / low software / on-chip / program analysis tools / /

Organization

EBP ECM / Computer Science Department / University of Crete / European Commission / University of Belfast Belfast / ECE Department / /

Person

J. Zhao / V / Crete / K. B. Theobald / S. Wallace / V / K. E. Moore / A. Jaleel / M. Lygerakis / V / J. Emer / S. C. Steely / Jr. / M. Martonosi / J. Wu / /

Position

unified scheduler for recursive and task dataflow parallelism / scalable locality-aware adaptive work-stealing scheduler for multi-core systems / unified scheduler / General / producer / scalable locality-aware adaptive work-stealing scheduler / model a state-of-the-art prefetch-aware replacement policy / Representative / scheduler / memory controller / programmer / power and area model for early-stage design space exploration / /

Product

Orion / /

ProgrammingLanguage

Cilk / C / /

ProvinceOrState

Oregon / /

Technology

FPGA / multicore processors / html / operating systems / specific scheduling algorithms / 5-stage routers / load balancing / java / coherence protocol / 32nm technology / caching / SDRAM / Simulation / /

URL

http /

SocialTag