![Central processing unit / Nios II / Joint Test Action Group / Instruction set / Nios embedded processor / Microarchitecture / Computer architecture / Computer hardware / Computer engineering Central processing unit / Nios II / Joint Test Action Group / Instruction set / Nios embedded processor / Microarchitecture / Computer architecture / Computer hardware / Computer engineering](https://www.pdfsearch.io/img/4d094046699d0137b83f564461c23faa.jpg)
| Document Date: 2014-02-14 18:17:39 Open Document File Size: 144,01 KBShare Result on Facebook
Company The Floating Point Hardware / Floating-Point Hardware / Altera Corporation / Feature Rounding Modes (1) NaN Floating-Point Hardware / / Country United States / / Facility GCC __builtin_custom_* facility / Implemented Implemented Multiplication Implemented Implemented Division Optional Implemented Square / be invoked directly using the GCC __builtin_custom_* facility / / IndustryTerm selection algorithm / software emulation / errant applications / software development tools / internal hardware / software debugger / target hardware / changes to any products / divide hardware / performance hardware / control applications / semiconductor products / software codes / target applications / / Person External Interrupt / Purpose Registers / / Position supervisor / Exception controller / parameter editor / eic_port_valid Program Controller & Address Generation Exception Controller Control Registers Instruction Cache Shadow Register Sets Tightly Coupled Instruction Memory Instruction / Processor parameter editor / / controller / programmer / / Product Nios II / / ProgrammingLanguage C / / Technology semiconductor / selection algorithm / JTAG / cache memory / operating system / / URL www.altera.com/common/legal.html / /
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