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City Report / Austin / / Company IBM / Compaq Western Research Laboratory / / / Facility Performance Processor Pipeline / University of Utah / University of Wisconsin-Madison / / IndustryTerm computer systems / 90nm technology / aggressive out-of-order processor / baseline processor / Circuit-level solutions / less energy / multicore processor technology / aggressive superscalar processor / out-of-order processors / in-order processor / attractive solution / conventional processor / energy / / Movie D. V / / Organization University of Utah / Rajeev Balasubramonian School of Computing / National Science Foundation / DED / U.S. Securities and Exchange Commission / University of Wisconsin / / Person J. S. Liptay / T. Monreal / V / / Position candidate for the eager register release policy / head / / ProgrammingLanguage FP / / ProvinceOrState Wisconsin / Utah / / Technology Alpha / aggressive out-of-order processor / 90nm technology / Memory Technology / aggressive superscalar processor / in-order processor / dual-threaded SMT processor / conventional processor / Implementable Simultaneous Multithreading Processor / SMT processor / multicore processor technology / out-of-order processors / cache Memory / RMT processor / caching / Simulation / Dynamic Superscalar Processors / baseline processor / Parallel Processing / Redundantly Threaded processor / Chip-level Redundantly-Threaded processor / CMP / / SocialTag 
Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor Niti Madan, Rajeev Balasubramonian School of Computing, University of Utah {niti, rajeev}@cs.utah.edu ∗ Abstract