IP Reuse: A Novel VHDL to Verilog Translation Flow Alessandro Fasan Andrea Fedeli STMicroelectronics, New Ventures Group, S.I.C.L., San Jose, CA, USA.

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Date: 2011-01-18 11:04:47		IP Reuse: A Novel VHDL to Verilog Translation Flow Alessandro Fasan Andrea Fedeli STMicroelectronics, New Ventures Group, S.I.C.L., San Jose, CA, USA. Add to Reading List Source URL: deepchip.com Download Document from Source Website File Size: 33,08 KB Share Document on Facebook