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CPU cache / Dynamic random-access memory / Synchronous dynamic random-access memory / Side channel attack / Microarchitecture / DIMM / CAS latency / Static random-access memory / SDRAM latency / Computer memory / Computer hardware / Computing


Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs Christopher W. Fletcher†∗, Ling Ren† , Xiangyao Yu† , Marten Van Dijk‡ , Omer Khan‡ , Srinivas D
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Document Date: 2014-01-23 18:47:27

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Company

MB LLC / Program Efficiency Trade / Aegis / Intel / the AES / /

Country

United States / /

Currency

pence / AMD / /

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Facility

University of Connecticut / Massachusetts Institute of Technology / /

IndustryTerm

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MarketIndex

SPEC / /

NaturalFeature

ORAM channel / /

Organization

University of Connecticut / Massachusetts Institute of Technology / Department of Defense / SESC / /

Person

Christopher W. Fletcher / Van Dijk / Ling Ren / Omer Khan / Srinivas Devadas / /

Position

model external DRAM power consumption / architect / controller and on-chip DRAM controller / conventional DRAM controller / official US policy / ORAM controller / functionally-equivalent ORAM controller / ORAM Accesses The ORAM controller / representative / DRAM controller / Controller / /

Product

Tmax / /

ProgrammingLanguage

FP / L / /

ProvinceOrState

Manitoba / /

RadioStation

Core / Watt / /

Technology

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