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Computer architecture / Central processing unit / Parallel Random Access Machine / NC / Computer memory / Parallel computing / Binary tree / Microarchitecture / Computer hardware / Computing / Models of computation


Oblivious Parallel RAM Elette Boyle∗ Technion Israel [removed] Kai-Min Chung
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Document Date: 2014-08-02 12:06:39


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Company

Mitzenmacher / Goodrich / Microsoft / /

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Event

FDA Phase / /

Facility

store K / /

IndustryTerm

secure processor / software protection / immediate applications / d-depth sorting network / actual solution / secure protocol / deterministic m-processor / important applications / m-processor / polynomial-time algorithm / multi-processor / sequential communications / client-server communications / secure hardware / above solution / fundamental applications / parallel processors / n-wire sorting network / intermediate solution / /

Organization

Defense Advanced Research Projects Agency / National Science Foundation / US Government / European Union / Cornell University / Technion / /

Person

Chung / Rafael Pass / Kai-Min Chung Academica Sinica / /

Position

first author / representative / /

Product

Concretely / BCP14 / ORAM / /

Technology

two-party secure protocol / RAM / 8 2.3 Sorting Networks Our protocol / polynomial-time algorithm / secure processor / requesting processors / Random Access / deterministic m-processor / 4 Secure Multi-Processor / shared memory / /

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