Static Prediction of Worst-case Data Cache Performance in the Absence of Base Address Information Diego Andrade, Basilio B. Fraguela and Ram´on Doallo University of A Coru˜na, Spain {dcanosa,basilio,doallo - Omar D. Conger - Document - PDFSEARCH.IO

First Page		Document Content
Date: 2009-02-13 05:39:10 Cache Compiler optimizations Computing Computer architecture Computer memory Computer engineering Locality of reference Software optimization Cache replacement policies Loop optimization Memory hierarchy Loop interchange		Static Prediction of Worst-case Data Cache Performance in the Absence of Base Address Information Diego Andrade, Basilio B. Fraguela and Ram´on Doallo University of A Coru˜na, Spain {dcanosa,basilio,doallo}@udc.es Add to Reading List Source URL: www.des.udc.es Download Document from Source Website File Size: 408,00 KB Share Document on Facebook

	Unit 3: Architecture, the Memory Hierarchy, and Caching •  Learning Objectives (unit) •  Leverage caching to overcome the differences in performance available at different levels of the memory hierarchy. DocID: 1v50l - View Document
	Memory Hierarchy for Web Search Grant Ayers* Stanford University Jung Ho Ahn* DocID: 1tNl9 - View Document
	MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency Rachata Ausavarungnirun1 Vance Miller2 Joshua Landgraf2 3 DocID: 1tLjk - View Document
	Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings* John Mellor-Crummey†, David Whalley‡, Ken Kennedy† † Department of Computer Science, MS 132 Rice Universit DocID: 1tKci - View Document