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Hardware description languages / Open Verification Methodology / SystemVerilog / Verilog / SystemC / Synopsys / Application-specific integrated circuit / E / Aldec / Electronic engineering / Electronic design automation / Hardware verification languages


RELEASED ON TUESDAY May 01, 2012 Job Title Senior Member Technical Staff Design & Verification Training
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Document Date: 2012-05-02 18:00:58


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File Size: 283,44 KB

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City

San Jose / /

Company

Type Location Compensation Benefits Organization About Doulos Inc / Synopsys / Doulos America Inc / /

Continent

North America / /

Facility

North America Headquarters / /

IndustryTerm

high-tech regions / verification consulting services / /

Organization

ASIC / FSA / /

Position

SoC designer / verification engineer / /

ProgrammingLanguage

Verilog / /

Technology

semiconductor / VHDL / ASIC / Verilog / /

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