| Document Date: 2013-09-02 15:24:09
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Company Synopsys / Sun Microsystems / / / Event FDA Phase / / Facility I/O Bridge / / IndustryTerm free software / interconnect protocol / Internet connection / / OperatingSystem Unix / Gentoo / Cygwin / GNU/Linux / Ubuntu / Microsoft Windows / / Organization ASIC / Clock Unit / / Position 0x99 DMA Controller 0x9A 0x9D 0x9E General Purpose I/O 0x9F Interrupt Controller / basic Interrupt Controller / 0x80 0x95 0x96 Real Time Clock 0x97 RAM Controller / Reset Controller and an Interrupt Controller / 0x96 Real Time Clock 0x97 RAM Controller 0x98 Wishbone Interconnect Arbiter / reset controller / 0x97 RAM Controller / Wishbone Interconnect Arbiter 0x99 DMA Controller 0x9A 0x9D 0x9E General / Time Clock 0x97 RAM Controller 0x98 Wishbone Interconnect Arbiter 0x99 DMA Controller / stream editor / Interrupt Controller / Controller / / Product Icarus version 0.8 / T1 / Icarus 0.8 / / ProgrammingLanguage Verilog / / PublishedMedium Icarus / / RadioStation Core / / Technology FPGA / PCX/CPX protocol / RAM / ASIC / Verilog / Unix / Linux / Wishbone interconnect protocol / Wishbone protocol / SIMULATION / PDF / / URL http /
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Simply RISC S1 Core Specification