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![]() | Document Date: 2012-11-22 12:13:36Open Document File Size: 1,39 MBShare Result on FacebookCitySan Francisco / Austin / /CompanyIBM Systems / Interconnection Networks / Morgan Kaufmann Publishers Inc. / Lawrence Berkeley National Laboratory / PROD (single and double precision) Software / Technology Group / /CountryUnited States / /CurrencyUSD / / /EventFDA Phase / /FacilityUniversity of Illinois / /IndustryTermnetwork management software / silicon technologies / parallel computing / computing protocols / coherence protocol / hub chips / levels metal / optical electronic devices / software stack / interconnect technology / sustained-petascale computing project / Internet Protocol / unreliable protocols / retransmission protocol / computing / non-uniform cluster computing / cache coherence protocol / /OperatingSystemL3 / /OrganizationBlue Waters Directorate / Defense Advanced Research Projects Agency / Section IV-D. D. Collectives Acceleration Unit / National Science Foundation / Collective Acceleration Unit / Nest Memory Management Unit / University of Illinois / US Federal Reserve / Project Office / /PersonBaba Arimilli / Jody Joyner / Jian Li / Scott Clark / Ravi Arimilli / C. Grothoff / V / CALE E XAMPLE / Marc Snir / Jerry Lewis / Jeongnim Kim / Vicente Chung / Ben Drerup / Wolfgang Denzel / Greg Bauer / Bill Kramer / Nan Ni / /PositionGeneral / author / /ProductHub chip / Hub / POWER7 / /ProvinceOrStateTexas / Illinois / /TechnologyObject-Oriented Programming / thirty-two Hub chips / IP / POWER7 chips / retransmission protocol / using Hub chips / operating system / silicon technologies / cache coherence protocol / 45 nm lithography Cu SOI technologies / Cmp / Hub chip / four POWER7 chips / Section V. The Hub chip / interconnect technology / Hardware-directed randomized route The Hub chip / coherence protocol / hub chips / implemented using 45 nm lithography Cu SOI technologies / /URLhttp /SocialTag |