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Central processing unit / Classes of computers / POWER4 / CPU cache / POWER3 / Microarchitecture / Instruction pipeline / IBM POWER / Instruction set / Computer architecture / Computer hardware / Computer engineering


by J. M. Tendler J. S. Dodson J. S. Fields, Jr.
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Document Date: 2005-12-28 21:05:45

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File Size: 430,49 KB

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City

Austin / /

Company

IBM / POWER4 / BP / Motorola / International Business Machines Corporation / Loads L3 / /

Currency

USD / /

Facility

FX pipeline / LD/ST pipeline / Somerset Design Center / pipeline Figure / BR pipeline / /

IndustryTerm

mainframe systems / pSeries systems / transistor-level tools / database applications / e - business / technology improvements / system service processor / highperformance computing requirements / software investment / computer-based and other information-service systems / process technology / earlier software / resultant systems / chip / recent systems / software hints / bridge chips / /

OperatingSystem

UNIX / AS/400 / L3 / /

Organization

Somerset Design Center / US Federal Reserve / /

Person

S. Dodson J. S. Fields / Jr. / ISS RF DC FX / Memory / ISS RF / /

Position

D0 WB Xfer WB Xfer WB Xfer WB / 8B 8B 16B 16B 16B 16B Fabric controller / Editor / GX controller / MP / controller 16B 16B 8B 4B 8B GX controller / 8B Performance monitor Loads 32B 8B SP controller / WB / fabric controller / L3 controller for the chip and / L2 cache controller / EA MP / controller / crack and group formation MP / EX MP / /

ProgrammingLanguage

DC / /

ProvinceOrState

Texas / Alabama / Manitoba / /

Technology

chip design / engines Chip / UNIX / two processors / JTAG / separate chip / 2002 Processor / lithography / one-third processor / process technology / I/O bridge chips / system service processor / same chip / one chip / 1 Loads L3 controller Memory controller 16B 16B Chip / service processor / caching / /

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