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POWER4 / CPU cache / Memory hierarchy / Microprocessors / IBM z10 / Montecito / Computer hardware / Computer memory / Computer architecture


Document Date: 2006-09-10 15:47:34

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City

POWER4 / Austin / /

Company

IBM / Artifical Neural Networks / IBM Server Group / D.C. Bossen L.C. / Hardware Hardware Hardware Hardware / Architectures Guest / /

Country

Germany / /

Currency

USD / /

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Event

Product Issues / /

Facility

Syracuse University / Northwestern University / ECC station / Rutgers University / Fraunhofer Institute of Autonomous Intelligent Systems / Digital Library / Processor Complex / /

IndustryTerm

storage devices / memory chip / large complex systems / extra hardware / check-bit modification algorithm / system software / technology assessment / redundant hardware / faulty hardware / silicon-on-insulator technology / predecessor systems / out-oforder processors / computing / larger systems / /

OperatingSystem

Unix / L3 / AIX / /

Organization

Rutgers University / Northwestern University / Fraunhofer Institute of Autonomous Intelligent Systems / SUE Service / Sigma Xi / Cooper Union / Syracuse University / /

Person

Karl E. Grosspietsch / Kevin Reick / Joel M. Tendler Kevin Reick / Douglas C. Bossen Joel / Joel M. Tendler / SUE UE / Douglas C. Bossen / /

/

Position

program director of technology assessment / lead performance analyst / Shared L2 cache L3 controller L3 directory Fabric controller / Editor / modules IOCC I/O channel controller / Interactive Executive / IEEE MICRO tem administrator / distinguished engineer / cache L1 instruction cache Shared L2 cache L3 controller / controller / programmer / distinguished engineer at the IBM Server Group / /

Product

cache line / part / hardware / bits / /

ProvinceOrState

Texas / /

PublishedMedium

the Art Review / /

Technology

Power4 processor / Power4 chip / affected processors / chip design / Four Power4 chips / Deconfigured processors / fixed algorithm / Unix / 9021 Processors / The Power4 chip / Power4 chips / OPERATING SYSTEM / four chips / check-bit modification algorithm / soft errors In Power4 CMOS technology / service processor / failed memory chip / 3081 Processor / out-oforder processors / directory Fabric controller Distributed switch L3 cache Processor / Memory slot L2 Chip / 0.18micron CMOS silicon-on-insulator technology / SUE Service processor / bus Memory slot Memory slot I/O slot L3 L2 Chip / using IBM’s 0.18micron CMOS silicon-on-insulator technology / /

URL

http /

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