Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University David May

First Page		Document Content
Date: 2004-10-09 05:59:28 Embedded systems Digital signal processors Reconfigurable computing Fabless semiconductor companies Parallel computing PicoChip Wearable computer EEMBC Icera Computing Classes of computers Electronics		Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University David May Add to Reading List Source URL: www.cs.bris.ac.uk Download Document from Source Website File Size: 20,40 KB Share Document on Facebook

	Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University David May DocID: 1a9Vz - View Document
	Power-efficiency, Performance, Programmability: Architecture and Design in Bristol David May, Bristol University David May DocID: 19MaR - View Document
	Success Story Lynx Design System Accelerates picoChip’s Migration to 40nm In the competitive consumer landscape, with each new generation of DocID: vNdb - View Document
	IEEE Signal Processing Magazine, Special Issue on Signal Processing on Platforms with Multiple Cores, Nov[removed]TRENDS IN MULTI-CORE DSP PLATFORMS DocID: 3Phd - View Document