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Intel® Xeon Phi™ Coprocessor Instruction Set Architecture Reference Manual September 7, 2012
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Document Date: 2013-02-26 05:23:46
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File Size: 2,25 MB
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Intel /
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United States /
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Store Unaligned Low From Int64 Vector /
Store Unaligned Low From Float64 Vector /
Store Unaligned Low From Int32 Vector /
Store Unaligned Low From Float32 Vector /
Store Aligned Float64 Vector /
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changes to speci ications and product /
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Core™ Duo /
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KMOV /
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4 Processor /
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http /
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X86 instructions
Instruction set architectures
Parallel computing
Central processing unit
Advanced Vector Extensions
Euclidean vector
SIMD
Sequence container
Vector
Computer architecture