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Parallel computing / Video compression / Block-matching algorithm / Inter frame / Field-programmable gate array / Systolic array / VHDL / Cell / Motion compensation / Asynchronous array of simple processors
Date: 2005-11-28 09:11:59
Parallel computing
Video compression
Block-matching algorithm
Inter frame
Field-programmable gate array
Systolic array
VHDL
Cell
Motion compensation
Asynchronous array of simple processors

1160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 12, NO. 12, DECEMBER 2002 Transactions Letters________________________________________________________________ Efficient and Configurable Full-Se

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