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Date: 2005-11-28 09:11:59Parallel computing Video compression Block-matching algorithm Inter frame Field-programmable gate array Systolic array VHDL Cell Motion compensation Asynchronous array of simple processors | 1160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 12, NO. 12, DECEMBER 2002 Transactions Letters________________________________________________________________ Efficient and Configurable Full-SeAdd to Reading ListSource URL: www.inesc-id.ptDownload Document from Source WebsiteFile Size: 808,92 KBShare Document on Facebook |
Chapter 1 CUSTOMIZABLE AND REDUCED HARDWARE MOTION ESTIMATION PROCESSORS Nuno Roma, Tiago Dias, Leonel Sousa AbstractDocID: 1q2wP - View Document | |
1160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 12, NO. 12, DECEMBER 2002 Transactions Letters________________________________________________________________ Efficient and Configurable Full-SeDocID: 1pi6S - View Document | |
IEEE TRANSACTIONS ON IMAGE PROCESSING, VOL. 6, NO. 11, NOVEMBERACKNOWLEDGMENT The authors thank the anonymous reviewers for their helpful comments. REFERENCESDocID: 1ooN8 - View Document | |
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