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Computing / Digital signal processing / Wireless networking / Field-programmable gate array / Embedded system / Digital signal processor / Very long instruction word / Wireless sensor network / Computer engineering / Electronic engineering / Parallel computing / Electronics


Low-Power Reconfigurable Architectures for HighPerformance Mobile Nodes Matthias Hanke, Tim Kranich, Mladen Berekovic, Yannis Papaefstathiou Technische Universität Braunschweig, Institut für Datentechnik, Hans-Sommerst
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Document Date: 2010-12-01 09:00:57

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File Size: 110,69 KB

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